Fabrication of electronic devices often requires multiple material deposition steps followed by patterning of deposited layers using photoresist-based techniques. These techniques can be expensive and time-consuming. In addition, deposition processes that are used in current fabrication methods often involve processing under vacuum, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD and CVD apparatuses are expensive and their use increases the costs of electronic device fabrication. Moreover, stress that is developed during deposition process and/or patterning process is often significant and leads to low manufacturing yield. Examples of such conventionally manufactured devices include photosensing elements in digital X-ray imager made from p-i-n photodiodes based on amorphous silicon (a-Si). Plasma-enhanced chemical vapor deposition (PECVD) process used for deposition of a thick amorphous silicon layer in such device often leads to peeling that is encountered after the pixel in the device is patterned. Finally, patterning of a thin film stack having multiple layers using lithographic technique often results in an “undercut” phenomenon due to different etching rates of different layers. Such undercut makes pixel connection in the following processing steps very difficult.
Accordingly, there is a need for electronic devices that can be fabricated with minimal patterning, with low internal stress among different layers and with reduced costs. There is also an interest in developing imaging elements in display and thin film sensor arrays with improved mechanical stability.